(1) Field of the Invention
This invention relates to monitoring and diagnostics of line processes used for the manufacture of semiconductor devices and more particularly to the measurement of critical dimensions of patterns by scanning electron microscopy.
(2) Description of Prior Art
Integrated circuits are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by first depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer which is then patterned and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. These circuits are then further interconnected by utilizing a second wiring level laid out upon a second insulating layer with via openings to the first level.
Depending upon the complexity of the overall integrated circuit, two to four levels of metallurgy are typically required to form the necessary interconnections and to direct the wiring to pads which make the external connections for the completed chip. Patterning of the contact and wiring levels is accomplished by photolithographic masking techniques accompanied by reactive-ion-etching(RIE).
A high density of circuit elements designed to sub-micron dimensions requires extremely tight dimensional control. Slight variations in processing conditions can generate significant dimensional deviations of the patterned features. To this end highly sensitive inspection methods are required to assure the dimensional and structural integrity of the design patterns.
The scanning electron microscope(SEM) has become a most valuable tool for examining and measuring patterns of sub-micron dimensions. Optical microscopy, even with the finest available microscopes, cannot resolve these images with sufficient accuracy to permit reliable measurements. Many times the objects can be discerned, but measurements to the accuracies required are not possible. The SEM permits such precise measurements to a remarkable degree and, as such, has become a vital tool for monitoring all facets of integrated circuit device manufacturing. In addition, other processing defects, such as small pockets of debris in via or contact openings, could go undetected by optical microscopy. In the SEM, however, they are revealed with extraordinary crispness and clarity.
The principle of the SEM requires placement of the specimen into a vacuum chamber where a focused electron beam impinges on the area being observed. The surface region of the specimen where the inspection is made must be electrically grounded within the SEM. Otherwise electrons from the beam accumulate on the surface and cause severe distortions of the image. Earlier SEMs with smaller chambers could only accept small specimens which were usually mounted onto aluminum pedestals using a conductive silver paste providing a good ground contact. Nevertheless, when the specimens have exposed layers of insulating films such as silicon dioxide or photoresist, local charging of these surfaces occurs, particularly when high beam accelerating voltages are required to obtain sufficient resolution. The result is image distortion sometimes even to the point of obliteration. The problem is avoided on disposable specimens by sputtering a thin layer of gold onto the specimen just prior to insertion into the microscope. This provides a conductive discharge path for the electrons. Herrick et.al U.S. Pat. No. 5,460,034 when examining epitaxial layers of AlGaAs/GaAs, found that a layer of gold 100 Angstroms thick improved their resolution from about 100 Angstroms to 60 Angstroms, by reducing charge build-up.
Current technology permits larger specimens to be placed into the SEM. Whole wafers taken from a production job may now be examined with the SEM and then re-inserted into the production line for continued processing. The SEM is used to examine photoresist images to determine if the feature dimensions are within specifications or if any residue or debris has remained in the developed pattern. The etched patterns in the structural layers are likewise inspected. The ability to insert whole wafers into the SEM for routine examination and measurement with minimal wafer handling risk makes this instrument ideal for production line inspections. However, depositing gold or some other conductive material to alleviate the charging problem is no longer an acceptable option. Since a conductive coating cannot be applied, other means must be taken to provide suitable discharge paths for the electron beam where such a problem exists.
The established features which need dimensional inspection include contact openings, via openings, polysilicon line widths, and metal line widths. Not only must these features be capable of measurement to high resolution but their edges must also verified to be of proper contour. To this end an SEM inspection is useful in establishing the thoroughness of certain processing steps viz. whether an etching operation has fully performed its objective, whether it has left remnants of un-etched material, or whether it has exceeded its objective by invading subjacent material. The accomplishment of these objectives is frequently impaired by electron charging when the feature area cannot provide an adequate discharge path.
It is frequently impossible to accurately inspect and measure pattern features in integrated circuit product dice with the SEM, especially at high resolution, because of the presence of p-n junctions and insulating layers. These barriers obstruct adequate conductive paths for the electrons to the substrate ground and result in image distortions due to charging. In addition, charge build-up in certain device areas such as field-effect-transistor gates, can cause damage to thin underlying gate oxides.
The effects of electron charging on the inspection and measurement of patterns with an SEM are illustrated by FIGS.1 and 2. In FIG. 1 there is shown a cross section of a wafer 50 having a layer of silicon oxide 52 and a layer of polysilicon 54. A layer of photoresist has been patterned over the polysilicon layer 54 to form a stripe 56 of width -d-. Such configurations are commonly encountered in the manufacture of integrated circuits. Not only is the SEM called upon to measure the line-width -d- to an accuracy of the order of tenths of a micron, but the integrity of the edge profile must also be established. FIG. 2A shows an SEM image of the photoresist line 56 in the absence of image charging, as would be observed when proper discharge paths are provided. The shading lines represent the darkness of the image. The edges of the photoresist stripe 56 are clearly discernible and the dotted lines 57 are the measurement reticles brought into alignment with the bottom edges of the stripe 56. The spacing -d- between these lines is well defined. Superimposed over the image is a secondary electron intensity scan 58, also provided by the SEM. This signal shows sharp peaks 58A which characterize the edges of the photoresist stripe 56.
In FIG. 2B there is shown the same feature as in FIG. 1 except that now severe image charging has occurred within the SEM. The reticle lines 57 are placed over this image to show the approximate locations of the edges of stripe 56 corresponding to the width -d- . The darker portions of the image now protrude inward, past these lines and only gradually lighten towards the center of the stripe 56. The edge defining peaks 58A of the secondary electron scan 58 are entirely absent. Images of the type shown in FIG. 2B are useless for pattern inspection and measurement purposes.
This invention teaches the use of independent and specially designed test structures having patterns corresponding to features of the integrated circuit dice and provided with conductive paths to drain away the electrons from the SEM electron beam.
Independent test structures for the observation of open circuits and short circuits caused by defects using an SEM have been describes by Mahant-Shetti et. al. U.S. Pat. No. 5,159,752. The patterns used by these authors to observe shorts consist of multiple small metal islands enclosed within the squares of a large metal grid structure and separated from the grid by dimensions comparable to those found in integrated circuit metal patterns. An island shorted to the grid by a defect produces a different intensity of secondary electrons and consequently a different shade in the SEM view. The structure for opens utilizes the same pattern but with a connecting stripe between the island and the grid metal. An open stripe caused by a defect results in a different shading of the island compared to the others.
An additional advantage of using independent test structures for SEM inspections rather than subjecting product structures to the SEM beam is that charge sensitive structures such as field-effect-transistor gates are not subjected to the risk of gate oxide damage. Lur et.al. U.S. Pat. No. 5,384,268 have dealt with such charging as it occurs during high energy ion implantation. Here a thin conductive layer of titanium is applied over the structures prior to the implant and removed by dry etching or wet chemical etching afterwards. Clearly, this would not be a practical solution for the frequent SEM inspections required during the interconnection level processing.